An instruction set, or instruction set architecture (ISA), is the part of the computer architecture related to programming, and may include the native data types, instructions, register architecture, addressing modes, memory architecture, interrupt and exception handling, and external input and output (I/O). The term instruction generally refers herein to macroinstructions—that is instructions that are provided to the processor (or instruction converter that translates (e.g., using static binary translation, dynamic binary translation including dynamic compilation), morphs, emulates, or otherwise converts an instruction to one or more other instructions to be processed by the processor) for execution—as opposed to micro-instructions or micro-operations (micro-ops)—that is the result of a processors decoder decoding macroinstructions.
The ISA is distinguished from the micro-architecture, which is the internal design of the processor implementing the instruction set. Processors with different micro-architectures can share a common instruction set. For example, Intel® Core™ processors and processors from Advanced Micro Devices, Inc. of Sunnyvale Calif. implement nearly identical versions of the x86 instruction set (with some extensions that have been added with newer versions), but have different internal designs. For example, the same register architecture of the ISA may be implemented in different ways in different micro-architectures using well-known techniques, including dedicated physical registers, one or more dynamically allocated physical registers using a register renaming mechanism (e.g., the size of a Register Alias Table (RAT), a Reorder Buffer (ROB) can be different for different processors), etc.
In conventional systems, the operation systems during a context switch save only the processor architectural states, but not the micro-architectural context. The architectural context generally includes contents of the architectural registers, which are visible to the software/programmer. The micro-architectural context includes contents of reorder buffers, retirement registers and performance monitoring counters, which are not visible to the software/programmer. The micro-architectural context contains performance data, such as power and energy usage data as well as other power management related parameters that can be used by the processor for power management. As a result, when a process or thread returns to execution, the processor needs to collect performance statistics from scratch. This results in inefficiency in processor operations during the initial period of a context switch.
Furthermore, most systems run power management control algorithms to manage power usage. These algorithms are typically based on the history of workload execution, under the assumption that the recent workload history is a good predictor to its behavior in the near future. However, when the workload execution enters a new phase, the recent past is no longer a good predictor. Additionally, when the workload execution enters a new phase, the micro-architectural context can be lost, which results in the power management control algorithms being unable to utilize the valuable performance data that can be obtained or derived from the micro-architectural context.